\doxysection{FLASH\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_f_l_a_s_h___type_def}{}\label{struct_f_l_a_s_h___type_def}\index{FLASH\_TypeDef@{FLASH\_TypeDef}}


FLASH Registers.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_aaf432a8a8948613f4f66fcace5d2e5fe}{ACR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_aa14871b2c6e5a8d2bf810641761a01be}{KEYR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a793cd13a4636c9785fdb99316f7fd7ab}{OPTKEYR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a26d5b300bc241e18ae7ab136215985fc}{CR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a5d830598943ff82b6be4ea8fc6c9bac8}{SR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a1616234c768f3942a208890a61b8489a}{CCR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a54026c3b5bc2059f1b187acb6c4817ac}{OPTCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_ad18a50ac6074ca8406e0b9331d8b37f8}{OPTSR\+\_\+\+CUR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_af1d843fc3ee9786b1599c9c4e5931f77}{OPTSR\+\_\+\+PRG}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_aff29b1647442c02fde8743bbf66a8405}{OPTCCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a42e424eff4ccc51798e7be73bf557438}{PRAR\+\_\+\+CUR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a186954ec5205f69e2252e9211c25e688}{PRAR\+\_\+\+PRG1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a77560cf333f29a0136bc491b71bcfb14}{SCAR\+\_\+\+CUR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a51b63ab13930aa7ec22de3d337e0174a}{SCAR\+\_\+\+PRG1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a1726ed8227420e2f6dc9a1ed487bdc8f}{WPSN\+\_\+\+CUR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_aba99064cf14051d008bcc38611f103bb}{WPSN\+\_\+\+PRG1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a29ee7e6c949d43de2b6bbdcc9345824d}{BOOT\+\_\+\+CUR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a51983c206864388043e4d7ee17853ecf}{BOOT\+\_\+\+PRG}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_ab9d2e4721cf8d544dd7e0abb2b797887}{RESERVED0}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a4fd52b83f3cacc9f208ecf5804a6e886}{CRCCR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a97ffd6724257a7f89e9b0802d704fc1e}{CRCSADD1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a213623a15e76ba66797fb6258dbe6d38}{CRCEADD1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a9c40b24687d5ac91a17c622a9248aac5}{CRCDATA}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_abc239ed3ca76715093c9fbdeeb0cf3c1}{ECC\+\_\+\+FA1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a984a26db6f5dd8bcbb6aac1096136d56}{RESERVED}} \mbox{[}3\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_ac5e49228dbc788694ff3b84f75631788}{OPTSR2\+\_\+\+CUR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_f_l_a_s_h___type_def_a3f0e9fa089ce5d62f8333ae7713c5d12}{OPTSR2\+\_\+\+PRG}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
FLASH Registers. 

\label{doc-variable-members}
\Hypertarget{struct_f_l_a_s_h___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_f_l_a_s_h___type_def_aaf432a8a8948613f4f66fcace5d2e5fe}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!ACR@{ACR}}
\index{ACR@{ACR}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ACR}{ACR}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_aaf432a8a8948613f4f66fcace5d2e5fe} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+ACR}

FLASH access control register, Address offset\+: 0x00 \Hypertarget{struct_f_l_a_s_h___type_def_a29ee7e6c949d43de2b6bbdcc9345824d}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!BOOT\_CUR@{BOOT\_CUR}}
\index{BOOT\_CUR@{BOOT\_CUR}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BOOT\_CUR}{BOOT\_CUR}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a29ee7e6c949d43de2b6bbdcc9345824d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+BOOT\+\_\+\+CUR}

Flash Current Boot Address for Pelican Core Register, Address offset\+: 0x40 \Hypertarget{struct_f_l_a_s_h___type_def_a51983c206864388043e4d7ee17853ecf}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!BOOT\_PRG@{BOOT\_PRG}}
\index{BOOT\_PRG@{BOOT\_PRG}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BOOT\_PRG}{BOOT\_PRG}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a51983c206864388043e4d7ee17853ecf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+BOOT\+\_\+\+PRG}

Flash Boot Address to Program for Pelican Core Register, Address offset\+: 0x44 \Hypertarget{struct_f_l_a_s_h___type_def_a1616234c768f3942a208890a61b8489a}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!CCR1@{CCR1}}
\index{CCR1@{CCR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CCR1}{CCR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a1616234c768f3942a208890a61b8489a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+CCR1}

Flash Control Register for bank1, Address offset\+: 0x14 \Hypertarget{struct_f_l_a_s_h___type_def_a26d5b300bc241e18ae7ab136215985fc}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!CR1@{CR1}}
\index{CR1@{CR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR1}{CR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a26d5b300bc241e18ae7ab136215985fc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+CR1}

Flash Control Register for bank1, Address offset\+: 0x0C \Hypertarget{struct_f_l_a_s_h___type_def_a4fd52b83f3cacc9f208ecf5804a6e886}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!CRCCR1@{CRCCR1}}
\index{CRCCR1@{CRCCR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CRCCR1}{CRCCR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a4fd52b83f3cacc9f208ecf5804a6e886} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+CRCCR1}

Flash CRC Control register For Bank1 Register , Address offset\+: 0x50 \Hypertarget{struct_f_l_a_s_h___type_def_a9c40b24687d5ac91a17c622a9248aac5}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!CRCDATA@{CRCDATA}}
\index{CRCDATA@{CRCDATA}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CRCDATA}{CRCDATA}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a9c40b24687d5ac91a17c622a9248aac5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+CRCDATA}

Flash CRC Data Register for Bank1 , Address offset\+: 0x5C \Hypertarget{struct_f_l_a_s_h___type_def_a213623a15e76ba66797fb6258dbe6d38}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!CRCEADD1@{CRCEADD1}}
\index{CRCEADD1@{CRCEADD1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CRCEADD1}{CRCEADD1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a213623a15e76ba66797fb6258dbe6d38} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+CRCEADD1}

Flash CRC End Address Register for Bank1 , Address offset\+: 0x58 \Hypertarget{struct_f_l_a_s_h___type_def_a97ffd6724257a7f89e9b0802d704fc1e}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!CRCSADD1@{CRCSADD1}}
\index{CRCSADD1@{CRCSADD1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CRCSADD1}{CRCSADD1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a97ffd6724257a7f89e9b0802d704fc1e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+CRCSADD1}

Flash CRC Start Address Register for Bank1 , Address offset\+: 0x54 \Hypertarget{struct_f_l_a_s_h___type_def_abc239ed3ca76715093c9fbdeeb0cf3c1}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!ECC\_FA1@{ECC\_FA1}}
\index{ECC\_FA1@{ECC\_FA1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ECC\_FA1}{ECC\_FA1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_abc239ed3ca76715093c9fbdeeb0cf3c1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+ECC\+\_\+\+FA1}

Flash ECC Fail Address For Bank1 Register , Address offset\+: 0x60 \Hypertarget{struct_f_l_a_s_h___type_def_aa14871b2c6e5a8d2bf810641761a01be}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!KEYR1@{KEYR1}}
\index{KEYR1@{KEYR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{KEYR1}{KEYR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_aa14871b2c6e5a8d2bf810641761a01be} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+KEYR1}

Flash Key Register for bank1, Address offset\+: 0x04 \Hypertarget{struct_f_l_a_s_h___type_def_aff29b1647442c02fde8743bbf66a8405}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!OPTCCR@{OPTCCR}}
\index{OPTCCR@{OPTCCR}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPTCCR}{OPTCCR}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_aff29b1647442c02fde8743bbf66a8405} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+OPTCCR}

Flash Option Clear Control Register, Address offset\+: 0x24 \Hypertarget{struct_f_l_a_s_h___type_def_a54026c3b5bc2059f1b187acb6c4817ac}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!OPTCR@{OPTCR}}
\index{OPTCR@{OPTCR}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPTCR}{OPTCR}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a54026c3b5bc2059f1b187acb6c4817ac} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+OPTCR}

Flash Option Control Register, Address offset\+: 0x18 \Hypertarget{struct_f_l_a_s_h___type_def_a793cd13a4636c9785fdb99316f7fd7ab}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!OPTKEYR@{OPTKEYR}}
\index{OPTKEYR@{OPTKEYR}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPTKEYR}{OPTKEYR}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a793cd13a4636c9785fdb99316f7fd7ab} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+OPTKEYR}

Flash Option Key Register, Address offset\+: 0x08 \Hypertarget{struct_f_l_a_s_h___type_def_ac5e49228dbc788694ff3b84f75631788}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!OPTSR2\_CUR@{OPTSR2\_CUR}}
\index{OPTSR2\_CUR@{OPTSR2\_CUR}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPTSR2\_CUR}{OPTSR2\_CUR}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_ac5e49228dbc788694ff3b84f75631788} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+OPTSR2\+\_\+\+CUR}

Flash Option Status Current Register 2, Address offset\+: 0x70 \Hypertarget{struct_f_l_a_s_h___type_def_a3f0e9fa089ce5d62f8333ae7713c5d12}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!OPTSR2\_PRG@{OPTSR2\_PRG}}
\index{OPTSR2\_PRG@{OPTSR2\_PRG}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPTSR2\_PRG}{OPTSR2\_PRG}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a3f0e9fa089ce5d62f8333ae7713c5d12} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+OPTSR2\+\_\+\+PRG}

Flash Option Status to Program Register 2, Address offset\+: 0x74 \Hypertarget{struct_f_l_a_s_h___type_def_ad18a50ac6074ca8406e0b9331d8b37f8}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!OPTSR\_CUR@{OPTSR\_CUR}}
\index{OPTSR\_CUR@{OPTSR\_CUR}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPTSR\_CUR}{OPTSR\_CUR}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_ad18a50ac6074ca8406e0b9331d8b37f8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+OPTSR\+\_\+\+CUR}

Flash Option Status Current Register, Address offset\+: 0x1C \Hypertarget{struct_f_l_a_s_h___type_def_af1d843fc3ee9786b1599c9c4e5931f77}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!OPTSR\_PRG@{OPTSR\_PRG}}
\index{OPTSR\_PRG@{OPTSR\_PRG}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OPTSR\_PRG}{OPTSR\_PRG}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_af1d843fc3ee9786b1599c9c4e5931f77} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+OPTSR\+\_\+\+PRG}

Flash Option Status to Program Register, Address offset\+: 0x20 \Hypertarget{struct_f_l_a_s_h___type_def_a42e424eff4ccc51798e7be73bf557438}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!PRAR\_CUR1@{PRAR\_CUR1}}
\index{PRAR\_CUR1@{PRAR\_CUR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PRAR\_CUR1}{PRAR\_CUR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a42e424eff4ccc51798e7be73bf557438} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+PRAR\+\_\+\+CUR1}

Flash Current Protection Address Register for bank1, Address offset\+: 0x28 \Hypertarget{struct_f_l_a_s_h___type_def_a186954ec5205f69e2252e9211c25e688}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!PRAR\_PRG1@{PRAR\_PRG1}}
\index{PRAR\_PRG1@{PRAR\_PRG1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PRAR\_PRG1}{PRAR\_PRG1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a186954ec5205f69e2252e9211c25e688} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+PRAR\+\_\+\+PRG1}

Flash Protection Address to Program Register for bank1, Address offset\+: 0x2C \Hypertarget{struct_f_l_a_s_h___type_def_a984a26db6f5dd8bcbb6aac1096136d56}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!RESERVED@{RESERVED}}
\index{RESERVED@{RESERVED}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED}{RESERVED}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a984a26db6f5dd8bcbb6aac1096136d56} 
uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+RESERVED\mbox{[}3\mbox{]}}

Reserved, 0x64 to 0x6C \Hypertarget{struct_f_l_a_s_h___type_def_ab9d2e4721cf8d544dd7e0abb2b797887}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_ab9d2e4721cf8d544dd7e0abb2b797887} 
uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+RESERVED0\mbox{[}2\mbox{]}}

Reserved, 0x48 to 0x4C \Hypertarget{struct_f_l_a_s_h___type_def_a77560cf333f29a0136bc491b71bcfb14}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!SCAR\_CUR1@{SCAR\_CUR1}}
\index{SCAR\_CUR1@{SCAR\_CUR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SCAR\_CUR1}{SCAR\_CUR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a77560cf333f29a0136bc491b71bcfb14} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+SCAR\+\_\+\+CUR1}

Flash Current Secure Address Register for bank1, Address offset\+: 0x30 \Hypertarget{struct_f_l_a_s_h___type_def_a51b63ab13930aa7ec22de3d337e0174a}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!SCAR\_PRG1@{SCAR\_PRG1}}
\index{SCAR\_PRG1@{SCAR\_PRG1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SCAR\_PRG1}{SCAR\_PRG1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a51b63ab13930aa7ec22de3d337e0174a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+SCAR\+\_\+\+PRG1}

Flash Secure Address to Program Register for bank1, Address offset\+: 0x34 \Hypertarget{struct_f_l_a_s_h___type_def_a5d830598943ff82b6be4ea8fc6c9bac8}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!SR1@{SR1}}
\index{SR1@{SR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR1}{SR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a5d830598943ff82b6be4ea8fc6c9bac8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+SR1}

Flash Status Register for bank1, Address offset\+: 0x10 \Hypertarget{struct_f_l_a_s_h___type_def_a1726ed8227420e2f6dc9a1ed487bdc8f}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!WPSN\_CUR1@{WPSN\_CUR1}}
\index{WPSN\_CUR1@{WPSN\_CUR1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WPSN\_CUR1}{WPSN\_CUR1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_a1726ed8227420e2f6dc9a1ed487bdc8f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+WPSN\+\_\+\+CUR1}

Flash Current Write Protection Register on bank1, Address offset\+: 0x38 \Hypertarget{struct_f_l_a_s_h___type_def_aba99064cf14051d008bcc38611f103bb}\index{FLASH\_TypeDef@{FLASH\_TypeDef}!WPSN\_PRG1@{WPSN\_PRG1}}
\index{WPSN\_PRG1@{WPSN\_PRG1}!FLASH\_TypeDef@{FLASH\_TypeDef}}
\doxysubsubsection{\texorpdfstring{WPSN\_PRG1}{WPSN\_PRG1}}
{\footnotesize\ttfamily \label{struct_f_l_a_s_h___type_def_aba99064cf14051d008bcc38611f103bb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t FLASH\+\_\+\+Type\+Def\+::\+WPSN\+\_\+\+PRG1}

Flash Write Protection to Program Register on bank1, Address offset\+: 0x3C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
